1. Technical Field
Various embodiments generally relate to a semiconductor package and a semiconductor system including the same, and more particularly, to a technology for improving a training precision in a dual die package (DDP) that shares pins.
2. Related Art
Semiconductor memory devices are being developed to increase the degree of integration and the operating speeds of the semiconductor memory devices. In order to increase the operating speeds of the semiconductor memory devices, a synchronous memory device has been developed. This synchronous memory device is capable of operating in synchronization with a clock signal received from outside a memory chip.
For example, an SDR (single data rate) synchronous memory device may use a single data pin to input and output data during a single clock cycle. In the SDR synchronous memory device, the input and output of the data is in synchronization with the rising edge of a clock signal.
However, the SDR synchronous memory device has difficulty in operating with systems which require high speed operations. Accordingly, a DDR (double data rate) synchronous memory device may be implemented. In a DDR synchronous memory device data is consecutively inputted and outputted through each data input/output pin, in synchronization with the rising edge and the falling edge of a clock signal.
As such, a bandwidth at least two times wider than the conventional SDR synchronous memory device may be realized without increasing the frequency of a clock signal, and thus, a high speed operation may be achieved.
Semiconductor devices are being designed to consume less power.
In particular, a memory for a high speed operation (for example, the Graphics Double Data Rate version 5 (GDDR5)) is being designed. The memory for the high speed operation may be capable of receiving addresses at not only the rising edge but also the falling edge of an external clock. Since it is possible to receive addresses twice for every one cycle, the number of address pins may be decreased in comparison to the conventional semiconductor memory device. An extra number of pins may be connected with a power supply voltage or a ground voltage to increase the operation speed of the semiconductor memory device.
In a semiconductor memory device such as a dynamic random access memory (DRAM), in order to achieve a larger capacity from a unit area, a plurality of semiconductor chips (or dies) may be stacked and then packaged.
A semiconductor memory device including only one semiconductor chip, packaged, is referred to as a single die package (SDP). Also, a semiconductor memory device including two semiconductor chips, stacked and packaged, is referred to as a dual die package (DDP). Further, a semiconductor memory device including four semiconductor chips, stacked and packaged, is referred to as a quad die package (QDP).
In a semiconductor device, in order to optimize an address setup/hold time, an address training operation for sweeping an address timing may be performed.
As the operating speed of a semiconductor device is increased and the cycle of a clock is shortened, alignment of operation timings among various commands, addresses and data applied to a memory device by a controller is regarded as an important factor for improving operational stability and precision.
In particular, in the case of a memory device requiring a substantially high data input/output speed, in order to prevent occurrence of an error, it is necessary to precisely align data input/output timings between a memory controller and a memory device.
In the case of a dual die package (DDP) having two dies are packaged into one, internal/external chip circumstances, that is, PVT (process, voltage and temperature) conditions may be different in the two dies.
That is to say, in the dual die package, two dies share address and command pins, but memory core regions in the respective dies operate separately from each other. Therefore, since the optimization timings of address setup/hold times are different according to PVT conditions in two dies, a training time is lengthened and the precision of the package may be degraded.